1. Field of the Invention
The invention relates to integrated circuit fabrication and more particularly to a method of performing in-line process checks on a product wafer.
2. Description of the Related Art
During production of integrated circuits, many circuits are formed on a single silicon wafer. Several wafers may be processed simultaneously in different chambers of the fabrication apparatus. The processed wafers contain integrated circuits that eventually become the final product, or chips. These wafers are often referred to as "product wafers." After wafer production, the chips are subjected to functional testing and then separated. Chips that pass functional testing are then packaged for sale as individual units.
The fabrication process comprises many steps, including deposition, masking, etching and other process steps. Defects are potentially and invariably introduced at each step of the process. Some types and quantity of defects are allowable and not fatal to the functionality of the final product. However, for process and quality control reasons, the defects are monitored.
Defects are introduced during deposition of desired materials such as silicon dioxide, silicon nitride, metal composites, polycrystalline silicon (polysilicon), and single crystal silicon. Additional defects are introduced during subsequent patterning steps such as masking and etching.
Electronic devices, chips, are formed upon "product" wafers subjected to the steps of a wafer fabrication process. "Control" wafers are processed independently of product wafers. The control wafers are used to measure total numbers of defects (defect count) introduced onto wafers during selected steps of the wafer fabrication process. For example, a masking step which forms features upon an exposed surface of a wafer typically involves depositing a layer of a desired material upon the exposed surface, applying a layer of photosensitive photoresist over the layer of the desired material, exposing a portion of the photoresist layer to light passed through a mask, removing the exposed portion (positive photoresist) or the unexposed portion (negative photoresist) of the photoresist layer (i.e., developing the photoresist layer), etching a portion of the layer of the desired material not covered by a remaining portion of the photoresist layer, and removing the remaining portion of the photoresist layer. The total number of defects introduced during the masking step may be determined by summing the number of defects introduced during each step involved in the masking step.
For the deposition step, the total number of defects upon an exposed surface of a control wafer is measured before subjecting the control wafer to the deposition step. Following the deposition step, the total number of defects present within and upon the deposited layer is measured. The total number of defects introduced during the deposition step is the total number of defects present within and upon the deposited layer following the deposition step minus the total number of defects present upon the exposed surface of the control wafer prior to the deposition step.
For the photoresist application step, the total number of defects upon an exposed surface of a control wafer is measured before processing the control wafer through the photoresist application apparatus. Due to peculiarities in the laser scanning measurement techniques, the photoresist layer is not applied to the exposed surface of the control wafer although the control wafer is otherwise processed in the photoresist application apparatus. Following the processing of the control wafer through the photoresist apparatus, the total number of defects present upon the exposed surface of the control wafer is measured. The total number of defects introduced during the photoresist application step is the total number of defects present upon the exposed surface of the control wafer following the processing of the control wafer through the photoresist application apparatus minus the total number of defects present upon the exposed surface of the control wafer prior to processing.
For the exposure step, the total number of defects upon an exposed surface of a control wafer is measured before subjecting the control wafer to the exposure step. Following the exposure step, the total number of defects present upon the exposed surface of the control wafer is measured. The total number of defects introduced during the exposure step is the total number of defects present upon the exposed surface of the control wafer following the exposure step minus the total number of defects present upon the exposed surface of the control wafer prior to the exposure step.
For the developing step, the total number of defects upon an exposed surface of a control wafer is measured before subjecting the control wafer to the developing step. Following the developing step, the total number of defects present upon the exposed surface of the control wafer is measured. The total number of defects introduced during the developing step is the total number of defects present upon the exposed surface of the control wafer following the developing step minus the total number of defects present upon the exposed surface of the control wafer prior to the developing step.
For the etching step, a control wafer is prepared by depositing a layer of the desired material upon an exposed surface of the wafer. The total number of defects upon and within the layer of the desired material is measured before subjecting the control wafer to the etching step. During the etching step, the layer of the desired material is substantially removed. Following the etching step, the total number of defects present upon the exposed surface of the control wafer is measured. The total number of defects introduced during the etching step is the total number of defects present upon the exposed surface of the control wafer following the etching step minus the total number of defects upon and within the layer of the desired material prior to the etching step.
For the resist removal step, the total number of defects upon an exposed surface of a control wafer is measured before subjecting the control wafer to the resist removal step. Following the resist removal step, the total number of defects present upon the exposed surface of the control wafer is measured. The total number of defects introduced during the resist removal step is the total number of defects present upon the exposed surface of the control wafer following the resist removal step minus the total number of defects present upon the exposed surface of the control wafer prior to the resist removal step.
As is readily apparent, defects introduced at earlier stages of the process have the potential to create additional defects down the line. When control wafer treatment differs from the product wafer treatment, uncertainties enter any tests conducted. It therefore is beneficial to conduct all testing on actual product wafers.